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November 2,1999
AN4003 PC POWER SUPPLY DESIGN WITH KA3511
Sang-Tae Im
1. GENERAL DESCRIPTION
The KA3511 is a fixed-frequency improved-performance pulse-width modulation control circuit with complete housekeeping circuitry for use in the secondary side of SMPS (Switched mode power supply). It contains various functions, which are precision voltage reference, over voltage protection, under voltage protection, remote on/off control, power good signal generator and etc.
OVP (Over voltage protection) section
It has OVP functions for +3.3V,+5V,+12V and PT outputs. The circuit is made up of a comparator with four detecting inputs and without hysteresis voltage. Especially, PT (Pin16) is prepared for an extra OVP input or another protection signal.
UVP (Under voltage protection) section
It also has UVP functions for +3.3V, +5V, +12V outputs. The block is made up of a comparator with three detecting inputs and without hysteresis voltage.
Remote on/off section
Remote on/off section is used to control SMPS externally. If a high signal is supplied to the remote on/off input, PWM signal becomes a high state and all secondary outputs are grounded. The remote on/off signal is transferred with some on-delay and off-delay time of 8ms, 24ms respectively.
Precision reference section
The reference voltage trimmed to 2% (4.9VPG (Power good signal generator) section
Power good signal generator is to monitor the voltage level of power supply for safe operation of a microprocessor. KA3511 requires few external components to accomplish a complete housekeeping circuits for SMPS. The KA3511 is available in a 22-pin dual in-line package.
Rev C, November 1999
1
ORDERING INFORMATION
Device KA3511 Package 22 DIP Operating Temperature -25C ~ 85C
22-DIP-400
FEATURES
* * * * * * * * * * * * * * * Complete PWM control and house keeping circuitry Few external components Precision voltage reference trimmed to 2% Dual output for push-pull operation Each output TR for 200mA sink current Variable duty cycle by dead time control Soft start capability by using dead time control Double pulse suppression logic Over voltage protection for 3.3V / 5V / 12V Under voltage protection for 3.3V / 5V / 12V One more external input for various protection (PT) Remote on/off control function (PS-ON) Latch function controlled by remote and protection input Power good signal generator with hysteresis 22-Pin dual in-line package
2. BLOCK DIAGRAM
RT CT 22 7 OSCILLATOR 8 PWM CONTROL CK 2 DELAY CONTROLLER Q 21 DEAD TIME CONTROLLER Q S 1.25V DEAD TIME CONTROL 19 5V INTERNAL BIAS VREF VCC 12 VREF Start Up 1 5V COMP3 9 1.8V COMP2 1.25V UVP COMP 1.25V 10 TPG 2.2uF TUVP 2.2uF 17 18 GND 0.6V 1.8V 0.6V COMP1 Ichag VREF PG GENERATOR VREF OVP COMP 1.25V 16 15 14 13 PT V12 V5 V3.3 0.1V 1.4V 11 PG R 5 TREM 6 REM (PS-ON) E D Q 20 C2 C1
COMP V5 V12
REMOTE ON/OFF
E/A(-) E/A(+)
3 4
DET
Rev C, November 1999
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3. PIN DESCRIPTION
C1 #22 E C2 DTC GND TUVP PT V12 V5 V3.3 Vref #12
KA3511
#1 VCC COMP E/A(-) EA(+) TREM REM RT CT DET TPG PG
#11
Pin No. 1 2 3 4 5 6 7 8 9 10 11
Name VCC COMP E/A(-) E/A(+) TREM REM RT CT DET TPG PG
I/O I O I I - I - - I - O
Function Supply voltage E/A output E/A (-) input E/A (+) input Remote on/off delay Remote on/off input Oscillation freq. setting R Oscillation freq. setting C Detect input PG delay Power good signal output
Pin No. 12 13 14 15 16 17 18 19 20 21 22
Name Vref V3.3 V5 V12 PT TUVP GND DTC C2 E C1
I/O O I I I I - - I O - O
Function Precision reference VTG OVP, UVP input for 3.3V OVP, UVP input for 5V OVP, UVP input for 12V Extra protection input UVP delay Signal ground Deadtime control input Output 2 Power ground Output 1
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Pin No. 1 2 3 4 5 6
Name VCC COMP E/A(-) E/A(+) TREM REM
Function Supply voltage. Operating range is 14V~30V. VCC =20V, Ta=25C at test. Error amplifier output. It is connected to non-inverting input of pulse width modulator comparator. Error amplifier inverting input. Its reference voltage is always 1.25V. Error amplifier non-inverting input feedback voltage.This pin may be used to sense power supply output voltage. Remote on/off delay. Ton/Toff=8ms/24ms (Typ.) with C=0.1F. Its high/low threshold voltage is 1.8V/0.6V. Remote on/off input. It is TTL operation and its threshold voltage is 1.4V. Voltage at this pin can reach normal 4.6V, with absolutely maximum voltage, 5.25V. If REM = "Low", PWM = "Low". That means the main SMPS is operational. When REM = "High", then PWM = "High" and the main SMPS is turned-off. Oscillation frequency setting R. (Test Condition RT=10k) Oscillation frequency setting C. (Test Condition CT=0.01F) Under-voltage detect pin. Its threshold voltage is 1.25V Typ. PG delay. Td=250ms (Typ) with CPG=2.2F. The high/low threshold voltage are 1.8V/0.6V and the voltage of Pin10 is clamped at 2.9V for noise margin. Power good output signal. PG = "High" means that the power is "Good" for operation and PG = "Low" means "Power fail". Precision voltage reference trimmed to 2%. (Typical Value = 5.03V) Over voltage protection for output 3.3V. (Typical Value = 4.1V) Over voltage protection for output 5V. (Typical Value = 6.2V) Over voltage protection for output 12V. (Typical Value = 14.2V) This is prepared for an extra OVP input or another protection signal. (Typical Value = 1.25V) Timing pin for under voltage protection blank-out time. Its threshold voltage is 1.8V and clamped at 2.9V after full charging. Target of delay time is 250ms and it is realized through external (C=2.2F). Signal ground. Deadtime control input. The dead-time control comparator has an effective 120mV input offset which limits the minimum output dead time. Dead time may be imposed on the output by setting the dead time control input to a fixed voltage, ranging between 0V to 3.3V. Output drive pin for push-pull operation. Power ground. Output drive pin for push-pull operation.
7 8 9 10 11 12 13 14 15 16 17
RT CT DET TPG PG Vref V3.3 V5 V12 PT TUVP
18 19
GND DTC
20 21 22
C2 E C1
Rev C, November 1999
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4. ABSOLUTE MAXIMUM RATINGS
Characteristic Supply voltage Collector output voltage Collector output current Power dissipation Operating temperature Storage temperature Symbol VCC VC1, VC2 IC1, IC2 PD TOPR TSTG Value 40 40 200 1 -25 to 85 -65 to 150 Unit V V mA W C C
TEMPERATURE CHARACTERISTICS
Value Characteristic Temperature coefficient of Vref (-25 CRev C, November 1999
5
5. ELECTRICAL CHARACTERISTICS (VCC =20V, TA =25C)
Value Characteristic REFERENCE SECTION Reference output voltage Line regulation Load regulation Temperature coefficient of Vref Short-circuit output current OSCILLATOR SECTION Oscillation frequency Frequency change with temperature(1) DEAD TIME CONTROL SECTION Input bias current Maximum duty voltage Input threshold voltage ERROR AMP SECTION Inverting reference voltage Input bias current Open-loop voltage gain Unit-gain bandwidth Output sink current Output source current PWM COMPARATOR SECTION Input threshold voltage OUTPUT SECTION Output saturation voltage Collector off-state current Rising time Falling time PROTECTION SECTION Over voltage protection for 3.3V VOVP1 3.8 4.1 4.3 V VCE(SAT) IC(off) TR TF IC=200mA VCC=VC=30V, VE=0V - - - - 1.1 2 100 50 1.3 100 200 200 V A ns ns VTH(PWM) Zero Duty Cycle - 4 4.5 V
(1) (1) (1)
Symbol Vref Vref.LINE Vref.LOAD Vref/T ISC fosc fosc/T
Test Condition Iref=1mA 14VMin. Typ. Max. Unit 4.9 - - - 15 - - 5 2.0 1.0 0.01 35 10 2 5.1 25 15 - 75 - - V mV mV %/C mA kHz %
IB(DT) DCMAX VTH(DT) Pin19 (DTC)=0V Zero Duty Cycle Max. Duty Cycle Vref(EA) IB(EA) GVO BW ISINK ISOURCE VCOMP=0.7V VCOMP=3.5V VCOMP=2.5V 0.5V- 45 - 0
-2.0 48 3.0 -
-10 50 3.3 -
A % V
1.20 1.25 1.30 - 70 - 0.3 -2.0 -0.1 95 650 0.9 -4.0 -1.0 - - - -
% A dB kHz mA mA
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5. ELECTRICAL CHARACTERISTICS (continued) Value Characteristic Over voltage protection for 5V Over voltage protection for 12V Input threshold voltage for PT Under voltage protection for 3.3V Under voltage protection for 5V Under voltage protection for 12V Charging current for UVP delay UVP Delay Time REMOTE ON/OFF SECTION REM on input voltage REM off input voltage REM off input bias voltage REM on open voltage REM on delay time REM off delay time REMOTE ON/OFF SECTION Detecting input voltage Detecting V5 voltage Hysteresis voltage 1 Hysteresis voltage 2 PG output load resistor Charging current for PG delay PG delay time PG output saturation voltage TOTAL DEVICE Standby supply current ICC - - 10 20 mA
(2)
Symbol VOVP2 VOVP3 VPT VUVP1 VUVP2 VUVP3 ICHG.UVP TD.UVP VREMH VREML IREML VREM(OPEN) Ton Toff VIN(DET) V5(DET) HY1 HY2 RPG ICHG.PG TD.PG VSAT(PG)
Test Condition - - - - - - C=2.2F, VTH =1.8V C=2.2F IREM = -200A - VREM =0.4V - C=0.1F C=0.1F - - COMP1, 2 COMP3 - C=2.2F, VTH =1.8V C=2.2F IPG =10mA
Min. Typ. Max. Unit 5.8 6.2 6.6 V V V V V uA ms V V mA V ms ms V V mV V k uA ms V 13.5 14.2 15.0 1.20 1.25 1.30 2.1 3.7 9.2 -10 100 2.0 - - 2.0 4 16 2.3 4.0 10 -15 260 - - - - 8 24 2.5 4.3 10.8 -23 500 - 0.8 -1.6 5.25 14 34
1.20 1.25 1.30 4.1 10 0.6 0.5 -10 100 - 4.3 40 1.2 1 -15 260 0.4 4.5 80 - 2 -23 500 0.2
Notes: 1. These Parameters, although guaranteed over their recommended operating conditions are not 100% tested in production. 2. REM on delay time (Pin6 REM: "L" "H"), REM off delay time (Pin6 REM: "H" "L")
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6. BLOCK DESCRIPTION & APPLICATION INFORMATIONS
6.1 OSCILLATOR BLOCK
Vref 12 VCC 1
12 RT CT 12
Figure 1. Oscillator RT, CT The KA3511 is a fixed-frequency pulse width modulation control circuit. An internal-linear sawtooth oscillator is frequency-programmable by two external components, RT and CT. The oscillator frequency is determined by 1.1 fosc = -------------------RT x CT
300K VCC=15V 100K IO - OSCILLATOR FREQUENCY
0.001F 10K CT=0.01F 1K 0.1F
1.0F 100 30 1K 2K 5K 10K 20K 50K 100K 200K 500K 1M
RT. TIMING RESISTANCE( )
Figure 2. Oscillator Frequency vs. Timing Resistance
6.2 PWM CONTROL BLOCK
Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip-flop clock-input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control-signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the timing diagram shown in Figure 4)
Rev C, November 1999
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RT CT
7 OSCILLATOR 8
Output Drive D Q Q1
2
COMP
4
PWM CONTROL
CK
Q
Q2
3
0.12V
1.25V
DEAD TIME CONTROLLER
Figure 3. PWM Control Block The control signals are external inputs that can be fed into the dead-time control, the error amplifier inputs, or the feedback input. The dead-time control comparator has an effective 120mV input offset which limits the minimum output dead time. Dead time may be imposed on the output by setting the dead time control input to a fixed voltage, ranging between 0V to 3.3V. The pulse width modulator comparator provides a means for the error amplifier to adjust the output pulse width from the maximum percent on-time, established by the dead time control input, down to zero, as the voltage at the feedback pin varies from 0.5V to 3.5V. The error amplifier may be used to sense power-supply output voltage, and its output is connect to noninverting input of the pulse width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop. When capacitor CT is discharged, a positive pulse is generated on the output of the dead time comparator, which clocks the pulse-steering flip-flop and inhibits the output transistors, Q1 and Q2. The pulse-steering flip-flop directs the modulated pulses to each of the two output transistors always for push-pull operation. The output frequency is equal to half that of the oscillator. The KA3511 has an internal 5.0V reference capable of sourcing up to 10mA of load current for external bias circuits. The reference has an internal accuracy of 2% with typical thermal drift of less than 50mV over an operating temperature range of -25C to 85C
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Feedback Dead-time control
Ct
Ck Q
Q
Output Q1
Output Q2
Figure 4. Operating Waveform
6.3 DEADTIME CONTROL for SOFT-START
12 3mA Vref + R1 47k 19 R2 1k C1 22uF
DTC Remote ON/OFF
Figure 5. Soft-Start Circuit Deadtime control for soft-start makes a power supply output rising time (Typ. 15ms) to reduce output ringing voltage for 3.3V, 5V, and 12V. If output rising time is too fast, output ringing voltage reaches OVP level. You can make a soft start function by add external components R1, R2 and C1 (refer to figure 5). At first the main power is turned-on, the deadtime control voltage keeps high state ( * = * 3V), and then go to the low voltage( * = * 105mV) that devided by R1, R2. R2 V DTC LOW = --------------------- x Vref(5V) = 104.9mV R1 + R2
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So Output Duty Ratio will change from the minimum duty ratio to the maximum duty ratio. Also, if the remote voltage is high, the deadtime control voltage will keep 3V (=3mA xR2 (1k)) by the internal 3mA current source for soft start. Therefore, when the remote voltage is low, the deadtime control voltage will be changed from 3V to almost ground potential. And its soft start time dependent on external capacitor C1.
6.4 OUTPUT VOLTAGE REGULATION
+5V +12V
2 R1 11k R2 33k R5 1k
COMP
E/A(+) 4 R3 2k C1 103 3 E/A(-) 1.25V
Vref PWM Control Comparator Err-Amp
R4 1k
Figure 6. Output Regulation Circuit +5V/+12V output voltages are determined by resistor ratio of R1,R2,R3 and R4. The resistor value can be changed by set condition and requirements. R5, C1 are the compensation circuit for stability. If output voltage (+5V or +12V) is increase, duty ratio of main power switch will be reduced by PWM control comparator signal and error amplifier output. Therefore the output voltage will be reduced. On the contrary, if output voltage (+5V or +12V) is reduce, duty ratio of main power switch will be increased by PWM control comparator signal and error amplifier output. Therefore the output voltage will be increased. So the output voltage of power supply will be regulated.
Rev C, November 1999
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6.5 OVP BLOCK
VO 3.3V 5V 13 14 12V 15
R101 PT D 16 A R102
R1
R3
R5
Vref=5V
B R2
C R4 R6 1.25V OVP COMP
SET of R/S Latch
R102, R102 : External Components
OVP function is simply realized by connecting Pin13, Pin14, Pin15 to each secondary output. R1, 2, 3, 4, 5, 6 are internal resistors of the IC. Each OVP level is determined by resistor ratio and the typical values are 4.1V/6.2V/14.2V.
OVP Detecting voltage for +3.3V
R1 + R2 R1 + R2 V OVP 1 ( +3.3V ) = -------------------- x V A = -------------------- x Vref = 4.1V R2 R2
OVP Detecting voltage for +5V
R3 + R4 R3 + R4 V OVP 2 ( +5V ) = -------------------- x V B = -------------------- x Vref = 6.2V R4 R4
OVP Detecting voltage for +12V
R5 + R6 R 5 + R6 V OVP 3 ( +12V ) = -------------------- x V C = -------------------- x Vref = 14.2V R6 R6 Especially, pin16 (PT) is prepared for extra OVP input or another protection signal. That is, if you want over voltage protection of extra output voltage, then you can make a function with two external resistors.
OVP Detecting voltage for PT
R 101 + R 102 R 101 + R 102 V PT = ------------------------------ x VD = ------------------------------ x Vref R 102 R 102 In the case of OVP, system designer should know a fact that the main power can be dropped after a little time because of system delay, even if PWM is triggered by OVP. So when the OVP level is tested with a set, you should check the secondary outputs (+3.3V/+5V/ +12V) and PG (Pin11) simultaneously. you can know the each OVP level as checking each output voltage in just time that PG (Pin11) is triggered from high to low.
Rev C, November 1999
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6.6 UVP BLOCK
3.3V 13 5V 14 12V 15
R1
R3 R5
Vref=5V
A B R2 C R2 R6 1.25V UVP COMP SET of R/S Latch
The KA3511 has UVP functions for +3.3V, +5V, +12V Outputs. The block is made up of three input comparators. Each UVP level is determined by resistor ratio and the typical values are 2.3V/4V/ 10V.
UVP Detecting voltage for +3.3V
R1 + R2 R1 + R2 V UVP 1 ( +3.3V ) = -------------------- x V A = -------------------- x Vref = 2.3V R2 R2
UVP Detecting voltage for +5V
R1 + R2 R1 + R2 V UVP 2 ( +5V ) = -------------------- x V A = -------------------- x Vref = 4V R2 R2
UVP Detecting voltage for +12V
R1 + R2 R1 + R2 V UVP 3 ( +12V ) = -------------------- x V A = -------------------- x Vref = 10V R2 R2
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6.7 REMOTE ON/OFF & DELAY BLOCK
Ton Vref 12 REM 5V Ion Rpull Trem 5 + Trem 0.1uF 2.2V COMP 0.6V 1.8V B C PWM Toff
COMP6 PG Block
Ion/Ioff
Q1
Q2
REM
6
Remote On/Off
Figure 9. Remote ON/OFF Delay Block Remote ON/OFF section is controlled by a microprocessor. If a high signal is supplied to the remote ON/OFF input (Pin6), the output of COMP6 becomes high status. The output signal is transferred to ON/OFF delay block and PG block. If no signal is supplied to Pin6, Pin6 maintains high status (=5V) for Rpull. When Remote ON/OFF is high, it produces PWM (Pin6) "High" signal after ON delay time (about 8ms) for stabilizing system. Then, all outputs (+3.3V, +5V, +12V) are grounded. When Remote ON/OFF is changed to "Low", it produces PWM "Low" signal after OFF delay time (about 24ms) for stabilizing the system. If REM is low, then PWM is low. That means the main SMPS is operational. When REM is high, PWM is high and the main SMPS is turned-off. ON/OFF delay Time can be calculated by following equation. 0.1F x 2V Ctrem x Von Ton = K 1 x -------------------------------------- 0.95 x ----------------------------- = 8.2msec 23A Ion 0.1F x 2.1V Ctrem x Voff Toff = K 2 x --------------------------------------- 0.8 x ---------------------------------- = 24msec 8A Ioff (K1, K2: Constant value gotten by test) In above equation, typical capacitor value is 0.1uF. If the capacitor is changed to larger value, it can cause malfunction in case of AC power on at remote High. Because PWM maintains low status and main power turns on for on delay time. So you should use 0.1uF or smaller capacitor.
Rev C, November 1999
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6.8 R/S FLIP FLOP (LATCH) BLOCK
R-S F/F (LATCH)
REMOTE ON/OFF OVP UVP ON/OFF DELAY Start-up R Delayed REMOTE NOR Q PG generator S R-S FF
PG BLOCK
Q NOR
Figure 10. R-S F/F Block Diagram OVP+ Low Low High High SET Low Low High Low RESET Low High Low High Qn+1 Qn High High Low Qn+1 Qn High Low High
There is a R-S F/F (Latch) circuit for shutdown operation in the KA3511. R-S F/F (Latch) is controlled by OVP, UVP, and some delayed remote ON/OFF signal. If any output of OVP or UVP is High, SET signal of R-S F/F is high status and it produces PWM "High" and main power is turned off. When remote signal is high, its delayed output signal is supplied to RESET port of R-S F/F and it produces SET low. So output Q is low status. At this time, PWM maintains high status by delayed remote high signal. After main power is turned-off by OVP/UVP and initialized by remote, if remote signal is changed to low, main power becomes operational. When you test KA3511, Remote ON/OFF signal should be toggled once for initializing.
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6.9 POWER GOOD SIGNAL GENERATOR
Vref +5V
12 14
VCC R15 1k R13 Vref R11 60k PG COMP COMP1 Q3 COMP3 Vref DET 9 COMP2 R12 4.7k R14 1.25V Remote ON/OFF + CPG 2.2uF
10
Ichg 11 PG
Q2
0.6V
1.8V
TPG
Figure 11. PG Signal Generator Block Power good signal generator curcuits generate "ON & OFF" signal depending on the status of output voltage to prevent the malfunctions of following systems like microprocessor and etc. from unstable outputs at power on & off. At power on, it produces PG "High" signal after some delay (about 250ms) for stabilizing outputs. At power off, it produces PG "Low" signal without delay by sensing the status of power source for protecting following systems. VCC detection point can be calculated by following equation. recommended values of R11, R12 are external components. R11 V DET = 1.25V x 1 + ---------- = 17.2V R12 COMP3 creates PG "Low" without delay when +5V output falls to less than 4.3V to prevent some malfunction at transient status, thus it improves system stability. When remote On/Off signal is high, it generates PG "Low" signal without delay. It means that PG becomes "Low" before main power is grounded. PG delay time (Td) is determined by capacitor value, threshold voltage of COMP3 and the charging current and its equation is as following. V PG x Vth 2.2F x 2V Td = ----------- ------------------------ = ----------------------------- 250ms Ichg Ichg 18A
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Considering the lightning surge and noise, there are two types of protections. One is a few seconds delay between TPG and PG for safe operation and another is some noise margin of Pin10. Noise_Margin_of_TPG = V10(max) - Vth(L) = 2.9V - 0.6V = 2.3V
7. ABOUT TEST METHOD
You can verify the KA3511 with a SMPS set. But you should pay attention to the device damage problem by increasing VCC. You should remove the sub-board after +5Vsb drops to 0V and VCC of KA3511 is grounded and then fan stops under the Remote Low. - OVP function of +3.3V/+5V/+12V You can test OVP for +3.3V/+5V/+12V by shorting Pin16 and Pin17 to GND. - UVP function of +3.3V/+5V/+12V You can simply test UVP for +3.3V/+5V/+12V by shorting Pin16 to GND. - OVP input threshold voltage for PT The test condition is remote "Low" and you increase the supply voltage of pin16 using a DC power supply. When the voltage is over 1.2 x V, main power supply will shutdown. So, you can measure the shutdown point of main power supply, and that will be a OVP input threshold voltage for PT. - Remote On/Off delay time You can measure the time difference of remote On/Off and the main power supply output as toggling the remote On/Off. - PG delay time In AC power-on time, secondary outputs are turned on and then after some delay time PG output is triggered from low to high. You can measure the time difference of +5V and PG in turn-on time.
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8. HOUSE KEEPING CIRCUIT
2k(1W) 2k(1W)
Standby Supply VCC=20V 12V 5V 0.01uF 15k
1
VCC
C1
22
2
COMP
E
21
3
11k 33k
E/A(-)
C2
20
4
1.8k
E/A(+)
DTC
19
5
0.1uF 1k +
TREM
6
Micom
REM
7
12k
K A 3 5 1 1
GND
18
TUVP
17
+ 2.2uF
RT
PT
16
8
+ 0.01uF
CT
V12
15
12V
9
DET
V5
14
5V
10
+ PG
TPG
V3.3
13
3V
2.2uF
11
PG
Vref
12
+ 1uF
Using the KA3511 requires few external components to accomplish a complete housekeeping circuits for SMPS.
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9. TYPICAL CHARACTERISTICS
VCC-I CC
0.014 5.010 0.012 0.010 0.008 0.006 0.004 0.002 0.000 0 10 20 30 40 5.002 -40 -20 0 20 40 60 80 100 120 140 5.008
Bandgap Reference Voltage Temperature Characteristic
Vref [V]
Supply Voltage [V]
ICC [A]
5.006 5.004
TEMP [C]
PIN19(Dead Time Control Voltage)-Duty Cycle
50 40 5 4 31.1% 21.8% 20 12.8% 10 0 0.0 0.5 1.0 1.5 2.0 2.5 2.73 3.0 1 0 3.6 3.8 3
OVP for 3.3V
Duty Ratio [%]
VPG [V]
30
2
4.0
4.2
4.4
4.6
Deadtime Control Voltage [V]
V3.3 [V]
OVP for 5V
7 6 5 5 4
OVP for 12V
VPG [V]
3 2 1 0 5.0 5.5 6.0 6.5 7.0
VPG [V]
4
3 2 1 0 14.0 14.2 14.4 14.6 14.8 15.0
V5 [V]
V12 [V]
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OVP for PT
5 4 5 4
UVP for 3.3V
VPG [V]
3 2 1 0 1.15 1.20 1.25 1.30 1.35
VPG [V]
3 2 1 0 21 22 23 24 25
Vpt [V]
Pin 13 (V3.3) Voltage [V]
UVP for 5V
5 4 5 4
UVP for 12V
VPG [V]
VPG [V]
3 2 1 0 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
3 2 1 0 9.0 9.5 10.0 10.5 11.0
Pin 14 (V5) Voltage [V]
Pin 15 (V12) Voltage [V]
Remote ON Charging Current
-0.000016 5 -0.000018 4 3 2 1 -0.000024 0 0 50 100 150 200 250 0
REM ON/OFF Vth
Irem [A]
-0.000020
-0.000022
VPG [V]
1
2
3
4
5
Vrem [V]
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Remote ON Open Voltage
5 4 5 4
Detecting V CC Voltage (DET)
Vrem [V]
VPG [V]
0 1 2 3 4 5
3 2
3 2 1
1 0 0 1.0 1.1 1.2 1.3 1.4 1.5
Pin 9 (DET) Voltage [V]
Detecting V5 Voltage
-0.000005 5 4 -0.000010
Charging Current for PG
VPG [V]
3 2 1 0 4.0 4.2 4.4 4.6 4.8 5.0
IPG [V]
-0.000015
-0.000020
0
20
40
60
80 100
120
140 160
Pin 14 (5V) Voltage [V]
Short Circuit Current
5 4
Hysteresis Voltage 2
-0.032
VPG [V]
0 100 200 300 400
Iref [A]
-0.033
3 2 1
-0.034
-0.035
0 0.0 0.5 1.0 1.5 2.0 2.5
Pin 10 (T PG) Voltage [V]
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21
Error Amp Sink Current
0.002 5 0.00
Reference Voltage
Isink & Isource [A]
4
Vref [V]
0 20 40 60 80 100 120 140
-0.002 -0.004 -0.006 -0.008
3 2 1 0 0 10 20 30 40
Supply Voltage [V]
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22
10. PACKAGE DIMENSION
9.14 0.20 0.360 0.008 1.05 ) 0.041 0.51 0.020 MIN 3.40 0.30 0.134 0.012
Rev C, November 1999
22-DIP-400
1
22 0.46 0.10 0.018 0.004 27.90 MAX 1.098 27.49 0.20 1.082 0.008
11
12
10.16 0.400
3.81 0.20 0.150 0.008 5.08 MAX 0.200
0.25 -0.05
0~15
+0.10
0.010 -0.002
+0.004
23
2.54 0.100
1.52 0.10 0.060 0.004
(
11. EXPERIMENTAL RESULT
CH1 : PS-ON CH2 : +5Vdc Output CH3 : PG Signal
Figure 12. Rising Time of +5Vdc Output Voltage
CH1 : PS-ON CH2 : +5Vdc Output CH3 : PG Signal
Figure 13. PG Signal Delay Time
Rev C, November 1999
24
CH1 : PS-ON CH2 : +5Vdc Output CH3 : PG Signal
Figure 14. Power Down Warning
CH1 : +3.3Vdc Output CH2 : +5Vdc Output CH3 : +12Vdc Output
Figure 15. No Load Protection
Rev C, November 1999
25
CH1 : Vcc CH2 : +5Vdc Output CH3 : PG Signal
Figure 16. Vcc, +5Vdc Output vs. PG Signal (High)
CH1 : Vcc CH2 : +5Vdc Output CH3 : PG Signal
Figure 16. Vcc, +5Vdc Output vs. PG Signal (Low)
Rev C, November 1999
26
12. APPLICATION CIRCUIT
47K R6 70K VCC R5 103 IC1 1 2 3 15K POWER ON + 0.1uF OUT REF 6 7 8 103 9 10 + 2.2uF 11 PG 100K + 4 5 Vcc COMP E/A(-) E/A(+) TREM REM RT CT DET TPG PG C1 E C2 DTC GND TUVP PT V12 V5 V3.3 Vref AR3511X D19 22 21 20 19 18 17 16 15 14 13 12 R3 56K + C6 22uF 12V OUT 5V OUT 3.3V OUT C2 R4 1.2K C1
C16 VR1
D9 CT
Reference
1. Power Electronics by Marvin J. Fisher 2. Principles Of Power Electronics by Kassakian
AUTHOR:
Sang-Tae Im: P-IC Application Team Tel. 82-32-680-1275 Fax. 82-32-680-1317 E-mail. sangtae.im@Fairchildsemi.co.kr
Rev C, November 1999
27
+
2.2uF
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

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